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1 ? fn6367.1 ISL97653A 5-channel integrated lcd supply the ISL97653A represents a fully integrated supply ic for lcd-tv applications. with an input operating range of 4v to 14v, both commonly used lcd-tv input supplies, 5v and 12v, are supported. an a vdd supply up to 20v is generated by a high-performance pwm boost converter with an integrated 4.4a fet. v on is generated using an integrated charge pump with on-chip dio des and can be modulated using an on-chip v on slice control circuit. v off is generated using an integrated charge pump cont roller. additionally, the chip allows for two logic supplies. a buck regulator with an included 2.5a high side switch is used for the main logic output and an internal ldo controller can be used to generate a second logic ldo output. to facilitate production test, an integrated hvs circuit is included which can provide high voltage stress of the lcd panel. an on-board temperature sensor is also provided for system thermal management control. the ISL97653A is packaged in a 40 ld 6mmx6mm qfn package and is specified for op eration over the -40c to +105c temperature range. features ? 5v to 14v input supply ? integrated 4.4a boost converter ? integrated v on charge pump and v on slice circuit ? integrated v off charge pump output ? integrated 2.5a buck converter ? ldo controller for an additional logic supply ? high voltage stress (hvs) test mode ? thermal shutdown ? 40 ld qfn (6mmx6mm) package ? pb-free (rohs compliant) applications ?lcd-tvs ? industrial/medical lcd displays pinout ISL97653A 40 ld 6x6 qfn top view ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL97653Airz ISL97653A 40 ld 6x6 qfn l40.6x6 ISL97653Airz-t* ISL97653A 40 ld 6x6 qfn tape and reel l40.6x6 ISL97653Airz-tk* ISL97653A 40 ld 6x6 qfn tape and reel l40.6x6 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 ldo-ctl ldo-fb pvin1 agnd prot lx2 lx1 pgnd2 pgnd1 temp comp fbb rset hvs en cdel ctl drn com pout pvin2 cb lxl1 lxl2 pgnd3 pgnd4 cm2 fbl vl vref fbn supn nout pgnd5 c1p c1n c2p c2n supp fbp data sheet february 21, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6367.1 february 21, 2008 absolute maxi mum ratings (t a = +25c) thermal information maximum pin voltages, all pins except below . . . . . . . . . . . . . . 6.5v lx1, lx2, supp, supn, nout, prot, c1n, c2n . . . . . . . . .24v pvin1, pvin2, lxl1, lxl2 . . . . . . . . . . . . . . . . . . . . . . . . . 16.8v en, ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5v drn, pout, com, c1p, c2p. . . . . . . . . . . . . . . . . . . . . . . . . .33v cb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21v recommended operating conditions input voltage range, vin . . . . . . . . . . . . . . . . . . . . . . . . 4v to 14v input capacitance, c in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10f boost output voltage range, a vdd . . . . . . . . . . . . . . . . . . . . +20v output capacitance, c out . . . . . . . . . . . . . . . . . . . . . . . . . . 3x22f boost inductor, l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h-10h v on output range, v on . . . . . . . . . . . . . . . . . . . . . . +15v to +30v v off output range, v off . . . . . . . . . . . . . . . . . . . . . . . -15v to -5v logic output voltage range, v logic . . . . . . . . . . . . +1.5v to +3.3v buck inductor, l2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h to 10h thermal resistance ja (c/w) jc (c/w) 6x6 qfn package (notes 1, 2) . . . . . . 32 8.6 operating ambient temperature range . . . . . . . . -40c to +105c operating junction temperature . . . . . . . . . . . . . . -40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = 12v, v boost = v supn = v supp = 15v, v on = 25v, v off = -8v, over temperature from -40c to +105c, unless otherwise stated. parameter description conditions min typ max unit supply pins v in supply voltage 4 14 v i s quiescent current enabled, no switching 4 5 ma disabled 2.7 3.5 ma f sw switching frequency 580 680 780 khz v ref reference voltage t a = +25c 1.190 1.215 1.240 v 1.187 1.215 1.243 v vlor undervoltage lockout threshold v l rising 3.4 3.55 3.7 v vlof undervoltage lockout threshold v l falling 2.9 3.0 3.2 v thermal shutdown temperature rising 150 c thermal shutdown hysteresis 20 c logic signals hvs, en, ctl logic input high 2.0 v logic input low 0.4 v pull-down resistance 115 174 215 k hvs, rset rset rset pull-down resistance hvs = high 200 i rset rset leakage current hvs = low, v rset = 1.2v 0.4 a a vdd boost dlim min duty cycle 8.5 12 % max duty cycle 90 % ISL97653A
3 fn6367.1 february 21, 2008 v boost boost output range 20 v eff boost boost efficiency vin = 12v, v boost = 15v 90+ % v fb boost feedback voltage t a = +25c 1.203 1.215 1.227 v 1.198 1.215 1.232 v i boost boost fet current limit 3.7 4.4 5.1 a r dson-boost switch on resistance 93 200 m v boost / v in line regulation - boost 0.08 0.15 % v boost / i out load regulation - boost load 100ma to 200ma 0.004 1 % logic buck eff buck buck efficiency vin = 5v, v logic = 3.3v 90+ % i buck buck fet current limit 1.9 4.0 a r dson-buck switch on resistance 150 210 m v ldo / i out load regulation - buck load 100ma to 500ma 0.5 1 % v fl feedback voltage t a = +25c 1.195 1.215 1.235 v 1.189 1.215 1.241 v v on charge pump iload_pcp_min external load driving capability v on = 24v (2x charge pump) 40 ma v on = 28v (3x charge pump) 40 ma v fbp feedback voltage, i on = 1ma t a = +25c 1.195 1.215 1.235 v 1.189 1.215 1.241 v r on (vsup_sw) on resistance of v sup input switch i(switch) = +40ma 10 17 r on (c1/2-)h high-side driver on resistance at c1- and c2- i(c1/2-) = +40ma 30 r on (c1/2-)l low-side driver on resistance at c1- and c2- i(c1/2-) = -40ma 4 10 v on load reg v on output load regulation i on = 10ma to 40ma 0.3 % v(diode) internal schottky diode forward voltage drop i(diode) = +40ma 700 800 mv v off charge pump iload_ncp_min external load driving capability supn>13.5v voff=-8v 100 120 ma v fbn feedback voltage, i off = 10ma t a = +25c 0.173 0.203 0.233 v 0.171 0.203 0.235 v r on (nout)h high-side driver on resistance at nout i(nout) = +60ma 10 r on (nout)l low-side driver on resistance at nout i(nout) = -60ma 5 v off load reg v off output load reg i off = 10ma to 100ma, t a = +25c 2.4 % ldo controller i drvp sink current v fbp = 1.1v, v ldo_ctl = 10v 12 15 ma ldo-fb feedback voltage w/transistor load 1ma t a = +25c 1.191 1.215 1.239 v 1.189 1.215 1.241 v electrical specifications v in = 12v, v boost = v supn = v supp = 15v, v on = 25v, v off = -8v, over temperature from -40c to +105c, unless otherwise stated. (continued) parameter description conditions min typ max unit ISL97653A
4 fn6367.1 february 21, 2008 fault detection thresholds t_off thermal shut-down (latched and reset by power cycle or en cycle) temperature rising 150 c vth_a vdd (fbb) a vdd boost short detection v(fbb) falling less than 0.9 v vth_pout (fbp) p out charge pump short detection v(fbp) falling less than 0.9 v vth_nout (fbn) n out charge pump short detection v(fbn) rising more than 0.4 v v on slice positive supply = v(pout) i(pout)_slice v on slice current from pout supply ctl = vdd, sequence complete 400 500 a ctl = agnd, sequence complete 150 200 a r on (pout-com) on resistance between pout-com ctl = vdd, sequence complete 5 10 r on (drn-com) on resistance between drn-com ctl = agnd, sequence complete 30 60 ron_com on resistance between drn-com and pgnd 200 260 400 prot i prot_on prot pull-down current or resistance when enabled by the start-u v prot > 0.9v 38 50 60 a v prot < 0.9v 500 760 1000 i prot_off prot pull-up current when disabled v prot < 20v 2 3 4 ma electrical specifications v in = 12v, v boost = v supn = v supp = 15v, v on = 25v, v off = -8v, over temperature from -40c to +105c, unless otherwise stated. (continued) parameter description conditions min typ max unit ISL97653A
5 fn6367.1 february 21, 2008 typical application diagrams a vdd buck v logic lxl1 fbl boost v on cp v off cp v off lx1 fbb rset fbp nout fbn vref pout comp cb lx2 c1p c1n c2p c2n pvin2 v on slice v on com drn cdel hvs ctl en vl pgnd1 pgnd2 lxl2 pgnd4 pgnd3 supp pgnd5 hvs ldo controller supn agnd temp sensor temp sequencing/fault control cm2 v in prot c4 220nf c5 220nf v logic2 ldo-ctl ldo-fb c8 4.7nf l 6.8h l1 r2 0 c2 4.7nf c3 22f x3 r3 55k r4 5k r5 20k r6 983k r7, 50k c9 470nf r8 1k r9 1k r10 c6 0.22f c0 10f r17 100k c7 4.7f r11 40k r12 328k c11 220nf c12 470nf c13 1f l 6.8h l2 c15 4.7f r13 2k r14 1.2k c14 20f c16 10nf r15 5.4k r16 5k d1 d2 d3 d4 c19 220nf 15 v logic q1 m0 pvin1 c22 0.1f c1 2.2f r17 30 32 33 27 26 36 15 16 17 18 24 25 14 9 38 1 7 5 6 37 31 39 40 8 4 3 2 13 11 10 12 22 23 20 21 19 28 29 34 35 r20 10k r21 75k r22 75k c30 optional internal regulator ISL97653A
6 fn6367.1 february 21, 2008 typical application diagrams (continued) + - + - + - + - + - + - + - + - control logic sawtooth generator current amplifier current limit comparator current limit threshold reference bias and sequence controller v ref gm amplifier uvlo comparator oscillator 0.75 v ref regulator supn 0.2v uvlo comparator 0.4v 0.75 v ref v ref p out r sense buffer control logic v ref sawtooth generator slope compensation gm amplifier supp current limit threshold current limit comparator supp c1- c1+ c2+ c2- p out ctl com buffer lx1 pgnd1 cb lxl1 cm2 fbl fbp fbn n out p vin1,2 en cdel p vin1,2 vl fbb cm1 pgnd2 lx2 current amplifier slope compensation v ref freq hvs logic rset hvs prot lxl2 drn 680khz vl ldo control logic2 ldo-ctl ldo-fb temp sensor temp ISL97653A
7 fn6367.1 february 21, 2008 typical performance curves figure 1. boost efficiency figure 2. boost load regulation figure 3. boost line regula tion figure 4. buck efficiency figure 5. buck load regulation figure 6. buck line regulation 70 80 90 100 0 500 1000 1500 i o (ma) efficiency (%) v in = 8v v in = 5v v in = 12v 0.0 0.1 0.2 0.3 0.4 0.5 0 500 1000 1500 i o (ma) load regulation (%) v in = 8v v in = 12v v in = 5v -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 5 6 7 8 9 1011 121314 v in (v) line regulation (%) i o = 100ma i o = 400ma 50 60 70 80 90 100 0 500 1000 1500 2000 i o (ma) efficiency (%) v in = 5v v in = 12v v in = 8v -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 500 1000 1500 2000 i o (ma) load regulation (%) v in = 5v v in = 12v v in = 8v 0.00 0.02 0.04 0.06 0.08 0.10 10 11 12 13 14 v in (v) line regulation (%) 5678 9 i o = 100ma i o = 400ma ISL97653A
8 fn6367.1 february 21, 2008 figure 7. von load regulation figure 8. voff load regulation figure 9. logic ldo load regulation figure 10. boost transient response figure 11. buck transient respons e figure 12. von slice operation typical performance curves (continued) -5 -4 -3 -2 -1 0 0 102030405060 i on (ma) load regulation (%) v on = 25v -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 102030405060 i on (ma) load regulation (%) v on = 25v -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 i ldo (ma) load regulation (%) v logic = 2.3v ch1 = a vdd (v boost )(500mv/div) ch2 = i o (boost)(200ma/div) 1ms/div 1ms/div ch1 = a vdd (v boost ) (100mv/div) ch2 = i o (boost) (100ma/div) 40?s/di ch1 = vctl (5v/div) ch2 = com (10v/div) ISL97653A
9 fn6367.1 february 21, 2008 figure 13. boost current limit figure 14. buck current limit pin descriptions pin number pin name description 1 pvin2 logic buck supply voltage. this is also the anal og supply from which the vl is generated. needs at least 1f bypassing. 2 cb logic buck boot strap pin. generate the gate driv e voltage for the n-channel mosfet by connecting a 1f cap to the switching node lxl1,2. 3, 4 lxl1, 2 logic buck switching node. source of the high side internal power n-channel mosfet for the buck. 5, 6 pgnd3,4 logic buck ground pin. 7 cm2 buck compensation pin. an rc network is reco mmended. increase r for better transient response at the expense of stability. 8 fbl logic buck feedback pin. high impedance input to regulate at 1.215v. 9 vl 5.25v internal regulator output. bypass with a 4.7f cap. ref voltage is generated from vl. 10 vref reference voltage output. bypass with a low va lued cap for transients - recommend 220nf. should not be greater than 5 times cdel cap to ensure correct start-up sequence. 11 fbn negative charge pump feedback pin. high impedance input to regulate to 0.203v. 12 supn negative charge pump supply voltage. can be the same as or different from a vdd. 13 nout negative charge pump driver output. 14 pgnd5 charge pump ground pin. 15 c1p charge pump capacitor 1, positive connection. 16 c1n charge pump capacitor 1, negative connection. 17 c2p charge pump capacitor 2, positive connection. 18 c2n charge pump capacitor 2, negative connection. 19 supp positive charge pump supply. can be the same as or different from a vdd. 20 fbp positive charge pump feedback pin. hi gh impedance input to regulate at 1.215v 21 pout v on charge pump output. 22 com high voltage switch control output. v on slice output. 23 drn lower reference voltage for v on slice output. usually connected to a vdd . 24 ctl input control pin for v on slice output. typical performance curves (continued) ch1 = lxl (400ns/div) ch2 = ilxl (400ns/div) ch1 = lxl (400ns/div) ch2 = ilxl (400ns/div) ISL97653A
10 fn6367.1 february 21, 2008 25 cdel v on slice control delay input . minimum 47nf. recommend 220nf but is only limited by leakage in the cap reaching a levels. 26 en chip enable (active high). can be driven to vin levels. 27 hvs high-voltage stress input select pin. high selects high voltage mode. 28 rset voltage set pin for hvs test. rset connects to ground in the high voltage mode - rset high. 29 fbb a vdd boost feedback pin. high impedance input to regulate at 1.215v. 30 comp boost compensation network pin. an rc netwo rk is recommended. increase r for better transient response at the expense of stability. an r = 0 is recommended for 4.4a boost requirements. 31 temp temperature sensor output voltage. an analog voltage from 0v to 3v for temperatures of -40c to +150c. 32, 33 pgnd1, 2 boost ground pins. 34, 35 lx1, 2 boost switch output. drain of the internal power nmos for the boost. 36 prot gate driver of the input protection switch. g oes low when en is high. can be used to modulate the passive input inrush current as shown by r 21 ,r 22 , and c 30 in the typical application diagram. 37 agnd analog ground. separate from pgnd?s and star under the chip. 38 pvin1 logic buck supply voltage.this is also the analog s upply from which the vl is generated. needs at least 1f bypassing. 39 ldo-fb ldo controller feedback. high impedance input to regulate at 1.215v. 40 ldo-ctl ldo control pin. gate drive for the external pnp bjt. pin descriptions (continued) pin number pin name description ISL97653A
11 fn6367.1 february 21, 2008 application information a vdd boost converter the a vdd boost converter features a fully integrated 4.4a boost fet. the regulator uses a current mode pi control scheme which provides good line regulation and good transient response. it can operate in both discontinuous conduction mode (dcm) at light loads and continuous mode (ccm). in continuous current mode, current flows continuously in the inductor du ring the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost soft-start function is digitally controlled within a fixed 10ms time frame during which the current limit is increased in eight linear steps. the boost converter uses a summ ing amplifier architecture for voltage feedback, current feedback, and slope compensation. a comparator looks at the peak inductor current cycle by cycle and term inates the pw m cycle if the current limit is triggered. since this comparison is cycle based, the pwm output will be released after the peak current goes below the cu rrent limit threshold. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k is recommended. the boost converter output voltage is determined by equation 2: where r 3 and r 4 are in the ?? on page 5. unless otherwise stated, component variables referred to in equations refer to the typical application diagram. the current through the mosfet is limited to 4.4a peak. this restricts the maximum out put current (average) based on equation 3: where il is peak to peak inductor ripple current, and is set by equation 4. f s is the switching frequency (680khz). table 1 gives typical values (worst case margins are considered 10%, 3%, 20%, 10% and 15% on v in , v o , l, f sw and i omax ): boost converter input capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. a ceramic capacitor with capacitance larger than 10f is recommended. the voltage rating of input capacitor shoul d be larger than the maximum input voltage. some capacitors are recommended in table 2 for input capacitor. boost inductor the boost inductor is a critic al part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h are recommended to match the internal slope compensation as well as to maintain a good transient response performance. the inductor must be able to handle the average and peak currents expressed in equations 5 and 6: some inductors are recommended in table 3. v boost v in ------------------ 1 1d ? ------------- = (eq. 1) a vdd r 3 r 4 + r 4 -------------------- - v fbb = (eq. 2) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 3) --------- d f s ---- - = (eq. 4) table 1. maximum output current calculation v in (v) v o (v) l (h) i omax (ma) 5 9 6.8 2215 5 12 6.8 1673 5 15 6.8 1344 12 15 6.8 3254 12 18 6.8 2670 table 2. boost converter input capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k table 3. boost inductor recommendation inductor dimensions (mm) vendor part number 10h/ 5.1a peak 13x13x4.5 tdk rlf12545t-100m5r1 5.9h/ 6a peak 12.9x12.9x4 sumida cdep12d38np-5r9mb-120 i lavg i o 1d ? ------------- = (eq. 5) i lpk i lavg i l 2 -------- + = (eq. 6) ISL97653A
12 fn6367.1 february 21, 2008 rectifier diode (boost converter) a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the re ctifier diode must meet the output current and peak inductor current requirements. the following table lists two recommendations for boost converter diode. output capacitor integrating output capacitors supply the load directly and reduce the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging an d discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts. table 5 shows some selections of output capacitors. pi loop compensation (boost converter) the boost converter of ISL97653A can be compensated by a rc network connected from comp pin to ground. c 2 = 4.7nf and r 2 = 0 to 10 . a rc network is used in the demo board. a higher capacitor value can be used to increase system stability. stability can be examined by repeatedly changing the load between 100ma and a max level that is likely to be used in the system being used. the a vdd voltage should be examined with an oscilloscope set to ac 100mv/div and the amount of ringing observed when the load current changes. reduce excessive ringing by reducing the value of the resistor in series with the cm1 pin capacitor. cascaded mosfet application a 20v n-channel mosfet is integrated in the boost regulator. for applications requ iring output voltages greater than 20v, an external cascaded mosfet is needed as shown in figure 15. the voltage rating of the external mosfet should be greater than a vdd . v in protection a series external p-fet can be used to prevent passive power-up inrush current from the boost output caps charging to v in - v schottky via the boost inductor and schottky diode. this fet also adds prot ection in the event of a short circuit on a vdd. the gate of the pfet (shown as m0 in the ?? on page 5) is controlled by prot. when en is low, prot is pulled internally to pvin1, thus m0 is switched off. when en goes high, prot is pulled down slowly via a 50a current source, switching m0 on. if the device is powered up wi th en tied to high, m0 will remain switched off until the voltage on vl exceeds the vlor threshold. once the voltage on prot falls below 0.6v and the step-up regulator is withi n 90% of its target voltage, prot is pulled down to ground via a 1.3k impedance. if a vdd falls 10% below regulation, the drive to prot reverts to a 50a current source. if a timed fault is detected, m0 is actively switched off. several additional external components can optionally be used to fine-tune th e function of pin prot (shown in the dashed box near m0 in application diagram). prot ramp rate can be controlled by adding a capacitor c30 between gate and source of m0. m0 gate voltage can be limited during soft-start by adding a resistor (~75k ) between gate table 4. boost converter rectifier diode recommendation diode v r /i avg rating package vendor fyd0504sa 50v/2a dpak fairchild semiconductor 30wq04fn 40v/3.5a dpak international rectifier table 5. boost output capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- + = (eq. 7) figure 15. cascaded mosfet topology for high output voltage applications intersil ISL97653A lx1, lx2 fbb a vdd v in ISL97653A
13 fn6367.1 february 21, 2008 and source of m0. in addition, a resistor can be connected between prot and the gate of m0, in order to limit the maximum v gs of m0 at all times. buck converter the buck converter is a step down converter supplying power to the logic circuit of the lcd system . the ISL97653A integrates a high voltage n-channel mosfet to save cost and reduce external component count. in the continuous current mode, the relationship between input voltage and output voltage as expressed in equation 8: where d is the duty cycle of the switching mosfet. because d is always less than 1, the output voltage of a buck converter is lower than input voltage. the peak current limit of buck converter is set to 2.5a, which restricts the maximum output current (average) based on equation 9: where i p-p is the ripple current in the buck inductor as shown in equation 10: where l is the buck inductor, f s is the switching frequency (680khz). feedback resistors the buck converter output voltage is determined by equation 11: where r 13 and r 14 are the feedback resi stors in the buck converter loop to set the output voltage current drawn by the resistor network should be li mited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feed back input bias current and the potential for noise being coupl ed into the feedback pin. a resistor network in the order of 1k is recommended. buck converter input capacitor input capacitance should support the maximum ac rms current which occurs at d = 0.5 and maximum output current. where i o is the output current of the buck converter. table 6 shows some recommendatio ns for input capacitor. buck inductor a 3.3h to 10h inductor range is recommended for the buck converter. besides the inductance, the dc resistance and the saturation current are also factors that need to be considered when choosing a buck inductor. low dc resistance can help maintain high efficiency. saturation current rating should be higher than 2a. here are some recommendations for buck inductor. rectifier diode (buck converter) a schottky diode is recommended for fast recovery and low forward voltage. the reverse voltage rating should be higher than the maximum input voltage. the peak current rating is 2.5a, and the average current is given by equation 13: where i o is the output current of buck converter. the following table shows some diode recommended. v logic v in --------------------- - d = (eq. 8) i omax 2.5a i p-p ? = (eq. 9) i pp v logic lf s ? --------------------- - 1d ? () ? = (eq. 10) v logic r 14 r 13 + r 14 -------------------------- - v fbl = (eq. 11) i acrms c in () d1d ? () ? i o ? = (eq. 12) table 6. input capacitor (buck) recommendation capacitor size vendor part number 10f/16v 1206 tdk c3216x7r1c106m 10f/10v 0805 murata grm21br61a106k 22f/16v 1210 murata c3225x7r1c226m table 7. buck inductor recommendation inductor dimensions (mm) vendor part number 4.7h/ 2.7a peak 5.7x5.0x4.7 murata lqh55dn4r7m01k 6.8h/ 3a peak 7.3x6.8x3.2 tdk rlf7030t-6r8m2r8 table 8. buck rectifier diode recommendation diode v r /i avg rating package vendor pmeg2020ej 20v/2a sod323f philips semiconductors ss22 20v/2a smb fairchild semiconductor i avg 1d ? () *i o = (eq. 13) ISL97653A
14 fn6367.1 february 21, 2008 output capacitor (buck converter) four 10f or two 22f ceramic capacitors are recommended for this part. the overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. pi loop compensation (buck converter) the buck converter of ISL97653A can be compensated by a rc network connected from cm2 pin to ground. c 8 = 4.7nf and r 20 = 10k rc network is used in the demo board. a larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. the stability can be optimized in a similar manner to that described in ?pi loop compensation (boost converter)? on page 12. bootstrap capacitor (c 13 ) this capacitor provides the supp ly to the high driver circuitry for the buck mosfet. the bootstrap supply is formed by an internal diode and capacitor combination. a 1f is recommended for ISL97653A. a low value capacitor can lead to overcharging and in turn damage the part. during very light loads, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. additionally, if v in - v buck < 1.5v, the internal mosfet pull-up device may be unable to turn-on until v logic falls. hence, there is a minimum load requirement in this case. the minimum load can be adjusted by the feedback resistors to fbl. charge pump controllers (v on and v off ) the ISL97653A includes 2 independent charge pumps (see charge pump block and connection diagram). the negative charge pump inverts the supn voltage and provides a regulated negative output voltag e. the positive charge pump doubles or triples the supp voltage and provides a regulated positive output volta ge. the regulation of both the negative and positive charge pump s is controlled by internal comparators that sense the ou tput voltage. these sensed voltages are then compared to scaled internal reference voltages. charge pumps use pulse width modulation to adjust the pump period, depending on the load present. the pumps can provide 100ma for v off and 40ma for v on . positive charge pump design consideration all positive charge pump diodes (d1, d2 and d3 shown in the ?negative charge pump block diagram? on page 16) for x2 (doubler) and x3 (tripler) modes of operation are included in the ISL97653A. during the chip start-up sequence the mode of operati on is automatically detected when the charge pump is enabled. with both c 7 and c 8 present, the x3 mode of operation is detected. with c 7 present, c 8 open and with c 1 + shorted to c 2 +, the x2 mode of operation will be detected. internal switches m1, m2 and m3 isolate p out from supp until the charge pump is enabled. this is important for tft applications that require the negative charge pump output (v off ) and a vdd supplies to be established prior to p out . the maximum p out charge pump current can be estimated from the following equations assuming a 50% switching duty: note: v diode (2 ? i max ) is the on-chip diode voltage as a function of i max and v diode (40ma) < 0.7v. table 9. buck output capacitor recommendation capacitor size vendor part number 10f/6.3v 0805 tdk c2012x5r0j106m 10f/6.3v 0805 murata grm21br60j106k 22f/6.3v 1210 tdk c3216x5r0j226m 100f/6.3v 1206 murata grm31cr60j107m i max 2x () min of 40ma or 2v ? supp 2 ? v diode 2i max ? () vv on () ? ? 22r onh r onl + ? () ? () -------------------------------------------------------------------------------------------------------------------------- 0.95a ? i max 3x () min of 40ma or 3v ? sup p 3 ? v diode 2i max ? () vv on () ? ? 23r onh 2r ? onl + ? () ? () -------------------------------------------------------------------------------------------------------------------------- 0.95v ? (eq. 14) ISL97653A
15 fn6367.1 february 21, 2008 in voltage doubler configuration, the maximum v on is as given by the following equation: for voltage tripler: v on output voltage is determined by the following equation: negative charge pump design consideration the negative charge pump consists of an internal switcher m1, m2 which drives external steering diodes d2 and d3 via a pump capacitor (c 12 ) to generate the negative v off supply. an internal comparator (a1) senses the feedback voltage on fbn and turns on m1 for a period up to half a clk period to maintain v (fbn) in regulated operation at 0.2v. external feedback resistor r 6 is referenced to v ref . faults on v off which cause v fbn to rise to more than 0.4v, are detected by comparator (a2) and cause the fault detection system to start the in ternal fault timer which will cause the chip to power down if the fault persists. the maximum v off output voltage of a single stage charge pump is: r 6 and r 7 in the typical application diagram determine v off output voltage. *although in the given typical application diagram, supp and supn are connected to a vdd , depending on a specific application, supn and/or supp could be connected to either a vdd or v in. figure 16. v on function diagram supp supp supp c1- pout fbp control c1+ c2- c2+ d3 d2 d1 m2 m4 m1 m3 m5 v ref 680khz x2 mode x3 mode both external connections and components 0.9v c7 c8 c14 c21 r8 r9 c22 error fb v on_max(2x) 2v supp v diode ? () ? 2i out 2r onh r onl + ? () ? ? ? = (eq. 15) v on_max(3x) 3v supp v diode ? () ? 2i out 3r onh 2r onl ? + ? ( ? ? ? = (eq. 16) v on v fbp 1 r 8 r 9 ------ - + ?? ?? ?? ? = (eq. 17) v off_max 2x () v supp ? v diode 2i out ? ++ = (eq. 18) r on nout () hr on nout () l + () ? v off v fbn 1 r7 r6 ------- - + ?? ?? v ref ? ? r7 r6 ------- - ?? ?? ? = (eq. 19) ISL97653A
16 fn6367.1 february 21, 2008 v on slice circuit the v on slice circuit functions as a three way multiplexer, switching the voltage on com between ground, drn and pout, under control of the start-up sequence and the ctl pin. during the start-up sequence, com is pulled to ground via an ndmos fet with r ds(on) of 260 ohms. after the start-up sequence has completed, ctl is enabled and acts as a multiplexer control such that if ctl is low, com connects to drn through a 30 internal mosfet, and if ctl is high, com connects to p out internally via a 5 mosfet. the slew rate of the switch cont rol circuit is mainly restricted by the load capacitance at com pin and is given by equation 20: where v g is the supply voltage applied to drn or voltage at p out , which range is from 0v to 30v. r i is the resistance between com and drn or p out including the internal mosfet r ds(on) , the trace resistance and the resistor inserted, r l is the load resistance of von slice circuit, and c l is the load capacitance of switch control circuit. in the typical application circuit, r 8 , r 9 and c 22 give the bias to drn based on equation 21: and r 10 can be adjusted to adjust the slew rate. v logic2 ldo an ldo controller is also integrated to provide a second logic supply. the ldo-ctl pin drives the base of an external transistor which should be sized for the current required. a resistor divider is used to set the output voltage by feeding back a reference voltage to ldo-fb. the internal feedback reference is 1.215v. hvs operation when the hvs input is taken high, the ISL97653A enters hvs test mode. in this mode, the output of a vdd is increased by switching rset to ground, and the avdd is set to: where r x is the value of r 4 in parallel with r 5 . avdd voltage higher than the maximum rating of the boost mosfet may damage the part. fault protection the ISL97653A incorporates a number of fault protection schemes. avdd, von, and voff are constantly monitored. if fault conditions are detected for longer than 1ms on these fb inputs, the device stops s witching and the outputs are disconnected. the ISL97653A al so integrates over temp and over current protection. supply sequencing when the input voltage v in is higher than 4v(uvlo), v ref , v logic, and v logic2 are turned on. v logic has a 9ms fixed soft-start at start-up. a vdd , v on , and v off are dependant on the en pin. figure 17. negative charge pump block diagram fault 0.2v clk en vdd supn fbn nout pgnd stop pwm control v ref r6 40k c20 820pf c19 100pf r7 328k v off (-8v) c13 470nf d2 d3 c12 220nf a2 0.4v a1 m1 m2 1.2mhz v t ------- - v g r i r l || () c l ------------------------------------ - = (eq. 20) v drn v on r 9 +avdd r 8 ? ? r 9 r + 8 --------------------------------------------------------- = (eq. 21) a vdd r 3 r x + r x -------------------- - v fbb = (eq. 22) ISL97653A
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6367.1 february 21, 2008 when en is taken high, voltage of pin prot and v off start ramping down. once the prot voltage falls below 0.9v, a vdd starts up with a 9ms fixed soft-start time. please note if v off is to start earlier than a vdd , then the supn needs to connect to vin, and vin voltage should be larger than v off absolute value. the delay between v off and a vdd can be controlled by c30 in the typical application diagram and is given by equation 23: the successful completion of the a vdd soft-start cycle triggers two simultaneous events. v on begins to ramp up and the voltage on cdel starts ramping up. when the voltage reaches 1.215v, v on slice starts. temperature sensor the ISL97653A also includes a temperature output for use in system thermal management control. the integrated sensor measures the die temp erature over the -40c to +150c range. output is in the form of an analog voltage on the temp pin in the range of 0v to 3v, which is proportional to the sensed die temperature. temperature accuracy is 8.5c over the -40c to +150c temperature range. the device should be disabled by the user when the temp pin output reaches 3v ( = +150c die junction). operation of the device between +125c and +150c can be tolerated for short periods, however in order to maximize the life of the ic, it is recommended that the effective continuous operating junction temperature of th e die should not exceed +125c. fault sequencing the ISL97653A has advanced overall fault detection systems including over current protection (ocp) for both boost and buck converters, under voltage lockout protection (uvlp) and ove r-temperature protection. once the peak current flowing through the switching mosfet of the boost and buck converters triggers the current limit threshold, the pw m comparator will disable the output, cycle by cycle, until th e current is back to normal. layout recommendation the device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors , boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref and v l bypass capacitors close to the pins. 3. reduce the loop with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point. 6. the exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. t delay v in 0.9v ? () c 30 50 a () ? = (eq. 23) v in vref v logic en a vdd v on v off v on slice * for demonstration only, not to scale prot cdel 2.8v 0.9v 1.215v figure 18. ISL97653A
18 fn6367.1 february 21, 2008 ISL97653A package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 3, 10/06 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal ? 0.0 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 ? 0 . 20 b 0.10 11 ma c 4 21 4 . 10 ? 0 . 1 0 . 90 ? 0 . c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05

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